In the package mounting of semiconductor integrated circuits, individual parts such as transistors and diodes, and especially recently, LSIs, there are desires for package size reduction, thickness reduction, and integration degree increase. LSI mounting techniques include the packages of the type having lead terminals incorporated in the package, and this type of packages, which is represented by QFNs (quad flat non-leaded packages), is one of the package types which are especially attracting attention from the standpoints of size reduction and integration degree increase. A process which is especially attracting attention in recent years among processes for QFN production comprises orderly arranging chips for OFNs on a die pad in a package pattern region of a lead frame, en bloc encapsulating the chips in the cavity of a mold with an encapsulating resin material, and then cutting the molding into individual QFN structures to thereby greatly improve the productivity per unit lead frame area. On the other hand, for attaining improved connection reliability in the mounting of semiconductor devices on substrates such as mother boards, there is a desire for a semiconductor device having the so-called standoff, i.e., a semiconductor device in which the conductor on the mounting side partly projects from the encapsulating resin.
Furthermore, semiconductor devices of a lead-less structure have been developed recently for the purpose of thickness reduction. The following process has, for example, been proposed as a process for producing such a lead-less semiconductor device. First, a metal foil is laminated to a base and etched so that the metal foil remains in given areas to form a die pad part 23a and conductive parts 23b on the base 20 as shown in FIG. 7. Subsequently, a semiconductor element 21 is bonded to the die pad part 23a through an adhesive layer 24, and the semiconductor element 21 is then electrically connected to the conductive parts 23b with wires 25. The resultant structure is subjected to transfer molding with a mold to thereby resin-encapsulate the structure so that only the space in which the semiconductor element 21 is electrically connected to the conductive parts 23b is filled with an encapsulating resin layer 26. Thereafter, the base 20 is separated from the encapsulating resin layer 26 to thereby produce a package including the encapsulated semiconductor element as shown in FIG. 8 (see document 1). In this process, since a die pad part 23a and conductive parts 23b are formed on a base 20, the conductive parts can have a reduced thickness. In addition, when such packages thus obtained through resin encapsulation with an encapsulating material are separated into individual packages, there is no need of cutting a lead frame. This process hence has an advantage that blade wear by dicing is slight.
Document 1: JP-A-9-252014